Programmable logic devices typically include blocks of random access memory (BRAMs) distributed on the device. A BRAM could comprise a single access port or two (or more) separate and independent ports (i.e. a dual port BRAM). Dual port BRAMS are typically symmetrical, where both ports are interchangeable. Data can be written through either port, or can be read from the same port that received the data or the other port. Each port is typically synchronous and requires a clock. During a read operation, a read address is registered on the read port, and the stored data is loaded into the output latches after the RAM access interval passes.
During a write operation, the write address is registered on the write port, and the data which is input is stored in the addressed location of the memory. Three different modes are used to determine data which is available on the output latches after a write operation. In a write-first mode, also commonly called a transparent write mode, input data is simultaneously written into memory and stored in the data output. In a read first mode, also called a read before write mode, data previously stored at the write address appears on the output latches, while the input data is being stored in memory. Finally, in a no-change mode, the output latches remain unchanged during a write operation. An example of a Block RAM having multiple write modes can be found in U.S. Pat. No. 6,373,779 entitled, “Block RAM having multiple configurable write modes for use in a field programmable gate array” (Issued Apr. 16, 2002).
However, the ability to read from and write to conventional BRAMS may be limited. As shown for example in the block diagram of a conventional dual port BRAM of FIG. 1, each port comprises a multiplexer read/write decode logic circuit. That is, the dual port BRAM 102 comprises a first port 104 having a single multiplexer read/write decode logic circuit 106, and a second port 108 also having a single multiplexer read/write decode logic circuit 110. The inputs of a conventional dual port BRAM are often configured to either write to or read from Port A and read from Port B. Because a common multiplexer decode circuit is used for both reading and writing for a given port, the read and write widths of the port are the same. That is, a single set of configuration inputs dictate the port width for both the read and write widths of a given port of the BRAM. Accordingly, the user must both read data having a certain width from a port and write data having the same width to that port.
Such a restriction limits the functionality of a BRAM. For example, if a port is used for writing, a certain width (e.g. 1 bit port width) for serially writing data to the port could be selected. However, when reading from the port, a different width (e.g. 32 bits) may be desired. Accordingly, the width for a port having a common multiplexer read/write decode logic circuit used for both reading and writing must be changed if a port is used for a different function having a different port width. That is, the width of the common multiplexer circuit must be selected depending upon whether the port is used for reading or writing. If Port A is set in a “×32” mode, both reading from and writing to the BRAM will occur in 32 bit widths through that port. In order to read or write with different widths, both Ports A and B of the BRAM must be used (i.e. one for reading in at one width and one for writing at a different width). Accordingly, there is a need for a random access memory enabling more efficient input and output of data.
While BRAMs on programmable logic devices are often used for conventional data storage, BRAMs can also be employed to provide a number of other functions. For example, a BRAM can be configured to function as a Content Addressable Memory (CAM), also referred to as an associative memory. CAMs are a class of parallel pattern matching circuits. In one mode, these circuits operate like standard memory circuits and may be used to store binary data. However, unlike standard memory circuits, a match mode of a CAM permits all of the data in the CAM device to be searched in parallel. As will be described in more detail below in reference to embodiments of the invention, a binary input word is compared with all of the words in the CAM. If any of the memory locations has the same binary bit pattern as the input word, an output signal is activated indicating that a match has occurred. In addition, the location that contains the same bit pattern is indicated. Accordingly, rather than outputting data as in a conventional memory, a CAM outputs the address of the memory location which stores a given input data word.
Because a content addressable memory is a digital circuit, it may be implemented in an FPGA or some other programmable logic device. However, conventional BRAMs implemented as CAMS have certain limitations. BRAMs implemented as CAMs generally include an array of registers to hold the data, and then use some collection of comparators to see if a match has occurred. However, using gate level logic such as programmable logic often results in a penalty. For example, because this CAM implementation in an FPGA relies on flip-flops as the data storage elements, the size of the circuit is restricted by the number of flip flops in the device.
Accordingly, there is also a need for a more efficient method of and circuit for implementing a CAM in a programmable logic device.